1. Field of the Invention
This invention relates to a semiconductor integrated circuit device. In particular, it relates to a semiconductor integrated circuit device which has enhanced or improved tolerance or resistance to electrostatic discharges, by using a protective circuit which is capable of preventing deterioration of an internal element due to the occurrence of an electrostatic discharge.
2. Description of Related Art
During the assembly of an LSI chip into a package or during the transportation of the LSI chip package, deterioration or destruction of a portion of the internal elements of the LSI chip may occur due to an electrostatic discharge (ESD). Electrostatic discharge refers to the electrostatic discharge of electrified individuals or objects into the LSI chip through the external terminals of the LSI chip package. Alternately, the LSI chip itself may become electrified at the time of assembly or during transportation, and discharged to individuals or objects. As a result, deterioration or destruction of a portion of the internal element of the LSI chip may occur.
For example, as shown in FIG. 10, in the output circuit 40 of a conventional semiconductor integrated circuit device, such as a gate array, the gate terminal 32a, the source terminal 32b and the substrate of an unused NMOS transistor 32 are connected to ground. The drain terminal 32c of the unused NMOS transistor 32 is attached to a pad 16, such as a bonding pad or the like. In addition, although not shown in FIG. 10, in an unused PMOS transistor, the gate terminal, the source terminal and the substrate are connected to a power supply, such as a power bus. The drain terminal of the unused PMOS transistor is connected to the bonding pad 16. In the unused transistor 32 which is thus connected, in its ordinary operating state, since the gate terminal 32a, the source terminal 32b and the substrate are connected to each other and to ground, the unused transistor 32 does not influence any of the other circuits.
Therefore, when a voltage due to an electrostatic discharge is applied to the drain terminal 32c of the unused transistor 32, the voltage potential at the drain terminal 32c increases. When the voltage potential at the drain terminal 32c exceeds a specified value, a breakdown occurs in the p-n junction between the drain and the substrate of the unused transistor 32. Alternately, a punch through will occur between the drain and source.
In this case, when an excessive reverse voltage is applied across the p-n junction, the p-n junction is unable to withstand the reverse voltage. A breakdown phenomena will thus occur. That is, an electron will receive kinetic energy from the electrical field. The electron having such kinetic energy will impact into an atom of the crystal lattice, cutting its crystal lattice bond, and creating an electron/hole pair. The created electron will impact into a neighboring atom of the crystal lattice, creating an additional electron/hole pair, thus producing what is known as impact ionization. Through the successive creation of electron/hole pairs, a drain current begins to flow.
If a breakdown occurs, the drain voltage increases corresponding to the increase in the drain current. However, if the drain voltage continues to increase, and the drain current continues to flow to the substrate, the electric potential of the substrate will increase. In this case, a forward current will begin to flow to the junction between the substrate and the source of the unused transistor 32. Thus, the substrate, because it is grounded, serves as a base, the drain serves as a collector, the grounded source serves as an emitter of a parasitic npn bipolar transistor. When the current of the bipolar transistor is added to the breakdown current toward the substrate, the drain current increases drastically.
Such a breakdown is generally characteristic of a transistor having a p-n junction. However, in the unused transistor 32 in which the gate terminal 32, the source terminal 32b and the substrate are grounded, when a breakdown occurs, it is often the case that the current flows in only a limited portion of a region along the width of the gate terminal. That is, the current density is high. Since a high temperature is produced in that limited portion of the gate terminal, even if the current is small, the unused transistor 32 deteriorates due to the excess heat. This means that even if the current caused by electrostatic discharge is small, i.e., even if the voltage of the ESD is low, the unused transistor 32 easily deteriorates. In other words, the electrostatic voltage resistance (ESD resistance) of the unused transistor 32 is low.
Therefore, one method for overcoming the above-outlined problem is proposed in "Dynamic Gate Coupling of NMOS Efficient Output ESD Protection", IEEE/IRPS, 1992, pp 141". FIG. 11 shows the proposed solution. As shown in FIG. 11, a protection circuit 22 for providing increased ESD resistance to electrostatic discharges uses a gate coupling effect. The protection circuit 22 comprises an NMOS transistor 24, as a thin oxide film transistor, which discharges the electrostatic discharge applied to the bonding pad 16 to ground. The thin oxide film transistor 24 has a thin gate insulation film. The protection circuit 22 further comprises an NMOS transistor 26, as a field transistor. The field transistor 26 has a thick gate insulating film and controls the thin oxide film transistor 24.
In this instance, the source terminal 26b of the field transistor 26 is grounded. The gate terminal 26a of the field transistor 26 is connected to the bonding pad 16. The drain terminal 26c of the field transistor 26 is connected to the gate terminal 24a of the thin oxide film transistor 24. In addition, the source terminal 24b of the thin oxide film transistor 24 is grounded, while the drain terminal 24c is connected to the bonding pad 16. Furthermore, the threshold voltage of the field transistor 26 is higher than the threshold voltage of the thin oxide film transistor 24. Furthermore, as shown by the dotted line in FIG. 11, a parasitic capacitance 28 exists between the drain and the gate of the thin oxide film transistor 24.
In the protection circuit 22, the threshold voltage of the field transistor 26 is high, and the field transistor 26 is ordinarily in an OFF state. Thus, during ordinary operational conditions, the thin oxide film transistor 24 is also in the OFF state in ordinary operation. Because the gate terminal 24a is not being driven by anything else, the gate terminal 24a is in a floating state and is fixed at a ground electric potential due to the leakage current of the junction between the drain and substrate of the field transistor 26. Thus, the thin oxide film transistor 24 does not influence any other circuit operation.
On the other hand, when a voltage due to an electrostatic discharge is applied to the protection circuit 22, then along with an increase in the voltage applied to the drain terminal 24a of the thin oxide film transistor 24, the parasitic capacitance 28 existing between the gate and the drain of the thin oxide film transistor 24 is electrically charged. When the gate voltage of the thin oxide film transistor 24 exceeds the threshold voltage, then the thin oxide film transistor 24 is switched into the ON state. A channel is formed between the drain and source of the thin oxide film transistor 24, and a current begins to flow through the thin oxide film transistor 24 to ground. Thus, the voltage applied to the bonding pad 16 (the pad voltage), which is thus also the drain voltage of the thin oxide film transistor 24 and the gate voltage of the field transistor 26, is grounded, and the voltage on the bonding pad is clamped to the voltage corresponding to the ON resistance value of the channel formed between the drain and source of the thin oxide film transistor 24 and the drain current.
If the thin oxide film transistor 24 is switched into the ON state, and the drain voltage of the thin oxide film transistor 24 exceeds a pinch off voltage, then the drain current of the oxide film transistor 24 reaches a saturated value. However, the drain voltage is increased by the electrostatic discharge. If the pad voltage exceeds a specified value, a breakdown occurs in the p-n junction between the drain and the substrate of the thin oxide film transistor 24. Thus, a drain current also begins to flow between the drain and the substrate. In other words, the drain current further increases drastically and the pad voltage will be clamped to the value corresponding to the resistance value between the drain and substrate and the drain current. Also, since the thin oxide film transistor 24 is in the ON state, in comparison with the unused transistor 32 in which the gate terminal 32a, the source terminal 32b and the substrate are also grounded, the breakdown occurs in the p-n junction between the drain and substrate of the thin oxide film transistor 24 at a voltage lower by a few volts.
In this case, since breakdown occurs in the thin oxide film transistor 24 when it is in the ON state, along with the operation as an NMOS transistor with a channel, a parasitic bipolar npn transistor is formed from the drain, which serves as a collector of the parasitic transistor, a grounded substrate, which serves as a base of the parasitic transistor, and a grounded source which serves as an emitter of the parasitic transistor, and is switched to the ON state. The pad voltage further increases corresponding to increase in the drain current. When the pad voltage exceeds the threshold voltage of the field transistor 26, the field transistor 26 is switched to the ON state. As a result, the gate voltage of the thin oxide film transistor 24 is pulled off to the ground potential. Since the thin oxide film transistor 24 which serves as an NMOS transistor is thus turned OFF, static electricity is subsequently discharged by a drain current between the drain and the substrate of the thin oxide film transistor 24 by means of the parasitic bipolar npn transistor of the thin oxide film transistor 24.
As indicated above, in the protection circuit 22, when a breakdown occurs, since the thin oxide film transistor 24, which operates as an NMOS transistor, is in the ON state, a uniform flow of current is possible along the width of the gate of the thin oxide film transistor 24. That is, the current density is low. Since there is no localized generation of heat within the thin oxide film transistor 24, even if there is a great amount of current, there will be no heat-related deterioration of the thin oxide film transistor 24. By this means, an improvement is made in the electrostatic voltage resistance of the thin oxide film transistor 24.
However, since, in this protection circuit 22, the gate terminal 26a of the transistor 26 is directly connected to the bonding pad 16, to which the voltage from the electrostatic discharge is applied, the transistor 26 must be a field transistor. That is, if an ordinary thin gate oxide film NMOS transistor is used as the transistor 26, the thin gate oxide film will be destroyed when a high voltage is applied to the gate terminal 26a. Furthermore, since the field transistor 26 must be used, in order to increase the parasitic capacitance 28 between the gate and the drain of the thin oxide film transistor 24, the area of the field transistor 26 must be increased.
In addition, the switching speed of the field transistor 26 is slow in comparison to an electrostatic pulse which has a short rise time. Thus, it is extremely difficult to adjust the timing for switching the thin oxide film transistor 24 into the OFF state. Conversely, in order to increase the switching speed of the field transistor 26, the size of the field transistor 26 must be further enlarged. In addition, since the gate insulating film of the field transistor 26 is thick, the threshold voltage of the field transistor 26 becomes higher. Thus, a very high voltage should be applied to the gate of the field transistor 26, to switch the field transistor 26 to the ON state. In other words, the operation of the thin oxide film transistor 24 as an NMOS transistor cannot be switched to the OFF state quickly enough. Therefore, the thin oxide film transistor 24 is exposed to an electrostatic pulse, specifically to a pulse with a high voltage of 30-40 volts, for an extended period. Furthermore, the thin oxide film transistor 24 and the field transistor 26 to which the high voltage is applied may easily be destroyed by the electrostatic discharge, which comprises yet another problem.